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1/17 september 2004 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. VNQ830A-e quad channel high side driver rev. 1 table 1. general features (*) per each channel n dc short circuit current: 6a n cmos compatible inputs n proportional load current sense n undervoltage and overvoltage shut-down n overvoltage clamp n thermal shut-down n current limitation n very low stand-by power dissipation n protection against: loss of ground and loss of v cc n reverse battery protection (**) n in compliance with the 2002/95/ec european directive description the VNQ830A-e is a quad hsd formed by assembling two vnd830a-e chips in the same so-28 package. the vnd830a-e is a monolithic device designed in | stmicroelectronics vipower m0-3 technology. the VNQ830A-e is intended for driving any type of multiple loads with one side connected to ground. this device has four independent channels and four analog sense outputs which deliver currents proportional to the outputs currents. figure 1. package active current limitation combined with thermal shut-down and automatic restart protect the device against overload. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (**) see application schematic at page 10 typ e r ds(on) i out v cc VNQ830A-e 60m w (*) 6a (*) 36v so-28 (double island) package tube tape and reel so-28 VNQ830A-e VNQ830Atr-e target specification
VNQ830A-e 2/17 figure 2. block diagram logic undervoltage overvoltage overtemp. 1 overtemp. 2 i lim2 demag 2 k i out2 i lim1 demag 1 k i out1 input 1 input 2 gnd 1,2 v cc 1,2 output 1 current sense 1 output 2 current sense 2 driver 2 driver 1 logic undervoltage overvoltage overtemp. 3 overtemp. 4 i lim4 demag 4 k i out4 i lim3 demag 3 k i out3 input 3 input 4 gnd 3,4 v cc 3,4 output 3 current sense 3 output 4 current sense 4 driver 4 driver 3
3/17 VNQ830A-e table 3. absolute maximum ratings figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage - 0.3 v - i gnd dc reverse ground pin current - 200 ma i out dc output current internally limited a i r reverse output current - 6 a i in input current +/- 10 ma v csense current sense maximum voltage -3 +15 v v v esd electrostatic discharge (human body model: r=1.5k w; c=100pf) - input - current sense - output - v cc 4000 2000 5000 5000 v v v v p tot power dissipation (per island) at t lead =25 c 6.25 w t j junction operating temperature internally limited c t stg storage temperature - 55 to 150 c v cc 1,2 gnd 1,2 input2 input1 current v cc 1,2 v cc 3,4 gnd 3,4 input4 input3 v cc 3,4 sense 1 v cc 3,4 output 3 output 3 output 3 output 4 output 1 output 1 output 1 output 2 v cc 1,2 output 4 output 4 output 2 output 2 current sense 2 current sense 3 current sense 4 1 14 15 28 connection / pin current sense n.c. output input floating x x x to ground through 1k w resistor x through 10k w resistor
VNQ830A-e 4/17 figure 4. current and voltage conventions table 4. thermal data (per island) note: (1) when mounted on a standard single-sided fr-4 board with 50mm 2 of cu per island (at least 35 m m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. note: (2) when mounted on a standard single-sided fr-4 board with 6cm 2 of cu per island (at least 35 m m thick) connected to all v cc pins. horizontal mounting and no artificial air flow. symbol parameter value unit r thj-lead thermal resistance junction-lead per chip 20 c/w r thj-amb thermal resistance junction-ambient (one chip on) 60 (1) 44 (2) c/w r thj-amb thermal resistance junction-ambient (two chips on) 46 (1) 31 (2) c/w i s1,2 i gnd1,2 output3 v cc1,2 gnd 1,2 input2 i out3 v cc1,2 v out4 output2 i out2 v out3 input1 i in1 cur. sense1 i sense1 output1 i out1 output4 i out4 v out2 v out1 i in2 i sense2 i sense3 i in4 i sense4 cur. sense2 cur. sense3 cur. sense4 input3 input4 v stat4 v in4 v sense3 v in3 v sense2 i in3 v in2 v sense1 v in1 i gnd3,4 gnd 3,4 i s3,4 v cc3,4 v cc3,4 v f1 (*) (*) v fn = v ccn - v outn during reverse battery condition
5/17 VNQ830A-e electrical characteristics (8v VNQ830A-e 6/17 electrical characteristics (continued) table 8. v cc - output diode (per each channel) table 9. logic input (per each channel) table 10. current sense (9v v cc 16v) (see fig. 5) note: 3. current sense signal delay after positive input slope. note: 4. sense pin doesnt have to be left floating. symbol parameter test conditions min typ max unit v f forward on voltage -i out =1.3a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v il input low level 1.25 v i il low level input current v in =1.25v 1 m a v ih input high level 3.25 v i ih high level input current v in =3.25v 10 m a v i(hyst) input hysteresis voltage 0.5 v v icl input clamp voltage i in =1ma i in =-1ma 6 6.8 -0.7 8v v symbol parameter test conditions min typ max unit k 1 i out /i sense i out1,3 or i out2,4 =0.25a; v sense =0.5v; other channels open; t j = -40c...150c 1000 1400 1900 dk 1 /k 1 current sense ratio drift i out1,3 or i out2,4 =0.25a; v sense =0.5v; other channels open; t j = -40c...150c -10 +10 % k 2 i out /i sense i out1,3 or i out2,4 =1.6a; v sense =4v; other channels open; t j =-40c t j =25c...150c 1280 1300 1500 1500 1800 1780 dk 2 /k 2 current sense ratio drift i out1,3 or i out2,4 =1.6a; v sense =4v; other channels open; t j =-40c...150c -6 +6 % k 3 i out /i sense i out1,3 or i out2,4 =2.5a; v sense =4v; other channels open; t j =-40c t j =25c...150c 1280 1340 1500 1500 1680 1600 dk 3 /k 3 current sense ratio drift i out1,3 or i out2,4 =2.5a; v sense =4v; other channels open; t j =-40c...150c -6 +6 % i sense analog sense leakage current v in =0v; i out =0a; v sense =0v; t j =-40c...150c v in =5v; i out =0a; v sense =0v; t j =-40c...150c 0 0 5 10 m a m a v sense max analog sense output voltage v cc =5.5v; i out =1.3a; r sense =10k w v cc >8v, i out =2.5a; r sense =10k w 2 4 v v v senseh analog sense output voltage in overtemperature condition v cc =13v; r sense =3.9k w 5.5 v r sense intrinsec sense pin resistance v cc =13v; t j >t tsd ; all channels open 400 w t dsense current sense delay response to 90% i sense (see note 3) 500 m s
7/17 VNQ830A-e figure 5. switching characteristics (resistive load r l =6.5 w ) table 11. truth table (per channel) conditions input output sense normal operation l h l h 0 nominal overtemperature l h l l 0 v senseh undervoltage l h l l 0 0 overvoltage l h l l 0 0 short circuit to gnd l h h l l l 0 (t j t tsd ) v senseh short circuit to v cc l h h h 0 < nominal negative output voltage clamp ll 0 v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) i sense t t 90% t d(off) input t 90% t d(on) t dsense
VNQ830A-e 8/17 table 12. electrical transient requirements iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 w 2 +25 v +50 v +75 v +100 v 0.2 ms 10 w 3a -25 v -50 v -100 v -150 v 0.1 m s 50 w 3b +25 v +50 v +75 v +100 v 0.1 m s 50 w 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 w 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 w iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
9/17 VNQ830A-e figure 6. waveforms sense n input n normal operation undervoltage v cc v usd v usdhyst input n overvoltage v cc sense n input n sense n load current n load current n load current n v ov v cc > v ov v cc < v ov short to ground input n load current n sense n load voltage n overtemperature input n sense n t tsd t r t j load current n input n load voltage n sense n load current n VNQ830A-e 10/17 figure 7. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / 2(i s(on)max ). 2) r gnd 3 (- v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k w) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input line is also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input pin is to leave it unconnected, while unused sense pin has to be connected to ground pin. load dump protection d ld is necessary (transil or mov) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. v cc1,2 output2 c. sense 1 d ld +5v r prot output1 r sense1,2,3,4 input1 c. sense 2 input2 m c r prot r prot r prot input3 input4 c. sense 3 c. sense 4 d gnd r gnd v gnd gnd1,2 gnd3,4 output3 r prot r prot r prot r prot v cc3,4 output4 note: channels 3 & 4 have the same internal circuit as channel 1 & 2.
11/17 VNQ830A-e . m c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the m c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of m c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of m c i/os. -v ccpeak /i latchup r prot (v oh m c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 3 20ma; v oh m c 3 4.5v 5k w r prot 65k w . recommended r prot value is 10k w
VNQ830A-e 12/17 so-28 double island thermal data figure 8. so-28 double island pc board table 13. thermal calculation according to the pcb heatsink area r tha = thermal resistance junction to ambient with one chip on r thb = thermal resistance junction to ambient with both chips on and p dchip1 =p dchip2 r thc = mutual thermal resistance figure 9. r thj-amb vs. pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 58mm x 58mm, pcb thickness=2mm, cu thickness=35 m m, copper areas: 0.5cm 2 , 3cm 2 , 6cm 2 ). chip 1 chip 2 t jchip1 t jchip2 note on off r tha x p dchip1 + t amb r thc x p dchip1 + t amb off on r thc x p dchip2 + t amb r tha x p dchip2 + t amb on on r thb x (p dchip1 + p dchip2 ) + t amb r thb x (p dchip1 + p dchip2 ) + t amb p dchip1 =p dchip2 on on (r tha x p dchip1 ) + r thc x p dchip2 + t amb (r tha x p dchip2 ) + r thc x p dchip1 + t amb p dchip1 1 p dchip2 10 20 30 40 50 60 70 01 234567 pcb cu he atsink area (cm ^2)/is land rthj_am b (c/w) r tha r thb r thc
13/17 VNQ830A-e figure 10. so-28 thermal impedance junction ambient single pulse figure 11. thermal fitting model of a double channel hsd in so-28 pulse calculation formula table 14. thermal parameter 0.01 0.1 1 10 100 1e-04 0.001 0.01 0.1 1 10 100 1000 tim e(s) zth(c/w ) 6 cm^2/ island 3 cm^2/ island 0,5 cm^2/island one channel on two channels on on same chip pd1 c1 r4 c3 c4 r3 r1 r6 r5 r2 c5 c6 c2 pd2 r14 c13 c14 r13 tj_1 tj_2 t_amb pd3 c7 r10 c9 c10 r9 r7 r12 r11 r8 c11 c12 c8 pd4 r16 c15 c16 r15 tj_3 tj_4 r17 r18 area/island (cm 2 ) 0.5 6 r1=r7=r13=r15 (c/w) 0.05 r2=r8=r14=r16 (c/w) 0.3 r3=r9 (c/w) 3.4 r4=r10 (c/w) 11 r5=r11 (c/w) 15 r6=r12 (c/w) 30 13 c1=c7=c13=c15 (w.s/c) 0.001 c2=c8=c14=c16 (w.s/c) 5.00e-03 c3=c9 (w.s/c) 1.00e-02 c4=c10 (w.s/c) 0.2 c5=c11 (w.s/c) 1.5 c6=c12 (w.s/c) 5 8 r17=r18 (c/w) 150 z th d r th d z thtp 1 d C () + = where d t p t =
VNQ830A-e 14/17 package mechanical table 15. so-28 mechanical data figure 12. so-28 package dimensions symbol millimeters min typ max a 2.65 a1 0.10 0.30 b 0.35 0.49 b1 0.23 0.32 c 0.50 c1 45 (typ.) d 17.7 18.1 e 10.00 10.65 e 1.27 e3 16.51 f 7.40 7.60 l 0.40 1.27 s 8 (max.)
15/17 VNQ830A-e figure 13. so-28 tube shipment (no suffix) figure 14. tape and reel shipment (suffix tr) all dimensions are in mm. base q.ty 28 bulk q.ty 700 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 a c b base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 16.4 n (min) 60 t (max) 22.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 16 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 7.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed reel dimensions
VNQ830A-e 16/17 revision history date revision description of changes sept. 2004 1 - first issue
17/17 VNQ830A-e information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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